This invention relates to an analog switch circuit of a CMOS (complementary metal oxide semiconductor) FET construction.
As shown in FIG. 1, an analog switch circuit of the CMOS type is fundamentally comprised of a transmission gate of the CMOS type. Specifically, the analog circuit is formed of a p channel MOS transistor P.sub.1 and an n channel MOS transistor N.sub.1, which transistors are connected in parallel. An input signal voltage Vin (FIG. 3C) is supplied to an input side node J.sub.1 of the p and n channel MOS transistors P.sub.1, N.sub.1. An output signal voltage Vout (FIG. 3D) is taken out from an output side node J.sub.2. The gate of the n channel MOS transistor N.sub.1 is supplied with a control signal .phi. (FIG. 3A). The gate of the p channel MOS transistor P.sub.1 is supplied with a control signal .phi. (FIG. 3B) having a phase which is opposite that of signal .phi.. A mirror capacitance C.sub.mN is present between the output side node J.sub.2 of the n channel MOS transistor N.sub.1 and the p channel MOS transistor P.sub.1, and the gate of said n channel MOS transistor N.sub.1. A mirror capacitance C.sub.mP is present between the output side node J.sub.2 and the gate of the p channel MOS transistor P.sub.1. A load capacitance C.sub.L is present between the output side node J.sub.2 and ground. FIG. 2 is a curve diagram showing the characteristics of a resistance against the input signal voltage Vin, which resistance arises between the input and output terminals of the subject switch circuit; and the characteristics of the resistance prevailing in the p channel MOS transistor P.sub.1 and n channel MOS transistor N.sub.1. With reference to FIG. 2, the abscissa denotes the input signl voltage Vin, and the ordinate represents a resistance value R. Roman numerals I and II respectively indicate the curves characterizing the resistances prevailing in the p channel MOS transistor P.sub.1 and the n channel MOS transistor N.sub.1. Roman numeral III shows a curve characterizing a resistance prevailing throughout the subject analog switch circuit; or, specifically, the resistance between the input and output terminals thereof. In this case, it is preferred that a resistance value R prevailing between the input and output terminals of the subject analog switch circuit be rendered constant throughout the entire range of the input signal voltage Vin. To stabilize said resistance value R, the conventional practice is to let the p channel MOS transistor P.sub.1 and n channel MOS transistor N.sub.1 have an equal resistance value. To attain this object, the p channel MOS transistor P.sub.1 is chosen in such a way as to have a channel width twice as broad as that of the n channel MOS transistor N.sub.1. However, the conventional procedure has a drawback, in that capacitance C.sub.mP assumes a value twice that of capacitance C.sub.mN ; and, as a result, the control pulse .phi. has its voltage level changed from that of the V.sub.DD voltage to that of the ground voltage GND, and the control pulse .phi. has its voltage level varied from that of the ground voltage GND to that of the V.sub.DD voltage. Therefore, when the transmission gate is rendered nonconductive, the output signal voltage Vout is offset from a correct value to the extent of .DELTA.V, in accordance with the difference between capacitance C.sub.mP and capacitance C.sub.mN.
The offset voltage V.sub.1 occurring when the control pulse .phi. has its logic level varied from "0" to "1", and the offset voltage V.sub.2 arising when the control pulse .phi. has its logic level changed from "1" to "0" are respectively expressed as follows: ##EQU1## Therefore, the output voltage Vout undesirably appears in a form offset to the extent of the sum .DELTA.V of voltages V.sub.1 and V.sub.2, which sum is expressed as: ##EQU2##